This application claims the priority benefit of Taiwan application serial no. 90126237, filed on Oct. 24, 2001.
1. Field of Invention
The present invention relates to a method for operating a multi-level memory. More particularly, the present invention relates to a method for operating a silicon nitride read-only memory (NROM).
2. Description of Related Art
The threshold voltage characteristic of an erasable and programmable read-only memory (EPROM), an electrical erasable and programmable read-only memory (EEPROM) and a flash memory is controlled by the total charges that are retained in the floating gate. A memory cell uses different threshold voltage ranges to define the various threshold voltage levels. Every level of the threshold voltage defines a different memory state of a multi-level memory cell.
FIG. 1 is a cross-sectional view showing the memory cell of a flash memory device according to the prior art. As shown in FIG. 1, a gate structure 102 includes, sequentially from bottom to top, an oxide layer 108, a polysilicon layer as the floating gate 104, an oxide layer 110, a nitride layer 112, an oxide layer 114 and a polysilicon layer as the control gate 106. The floating gate 104 is in a xe2x80x9cfloating statexe2x80x9d, which is not connected with any line and is used for charge storage. The control gate 106 controls the storage and retrieval of information. The formation of the gate structure 102 thus requires a multiple of masking processes. Moreover, an additional voltage is applied to the control gate during the programming of the flash memory device 100 to provide the bias that is required for the programming of the flash memory device 100.
The aforementioned flash memory 100 (as shown in FIG. 1) typically can store a single bit of data, for example, a logic xe2x80x9c0xe2x80x9d state or a logic xe2x80x9c1xe2x80x9d state. FIG. 2 is a diagram illustrating the method for detecting the logic xe2x80x9c0xe2x80x9d state or the logic xe2x80x9c1xe2x80x9d state by a memory cell. During a reading operation, a voltage Vread is applied to the gate. If the voltage Vread is smaller than the threshold voltage Vt, no current would travel through the source region and the drain region of the memory cell, and a logic state of xe2x80x9c0xe2x80x9d is determined. If the voltage Vread is greater than the threshold voltage Vt, a large current would travel through the source region and the drain region of the memory cell to determine a logic state of xe2x80x9c1xe2x80x9d.
The development of the high-density flash memory cell provides four memory states in a single bit of memory. FIG. 4 illustrates the distribution of the three threshold voltages (Vt1, Vt2, Vt3) of a memory cell of a high density flash memory device. Similar to the conventional memory that stores a single bit of memory, a voltage Vread is applied to the gate during the reading of a memory cell. If Vread is less than Vt1, a current is traveled through the source region and the drain region of the memory device to determine a logic state of xe2x80x9c00xe2x80x9d. If Vread is greater than Vt1 but is less than Vt2, as in FIG. 3, a higher current would travel through the source region and the drain region of the memory cell to determine a logic state of xe2x80x9c01xe2x80x9d. The logic state of xe2x80x9c10xe2x80x9d is determined if the Vread voltage is between the threshold voltage Vt2 and Vt3 and the logic state xe2x80x9c11xe2x80x9d is determined if the Vread voltage is higher than Vt3, respectively.
Referring again to FIG. 1, an additional voltage is applied to the control gate during the programming of the flash memory device 100 to provide the bias that is required for the programming of the flash memory device 100. In order to reduce the bias that is required for the programming of the flash memory device 100, an additional polysilicon layer is formed between the oxide layer 108 and the floating gate 104 to increase the coupling ratio of the floating gate 104 and to reduce the required bias during the programming of the flash memory device 100. An additional ion implantation process (as illustrated by the slanted line region 120 in FIG. 1) may also performed in the regions near the source region 118 and the drain region 116, respectively. The additional ion implantation would increase the erasure capability of the flash memory device 100. The additional implantation process, however, would complicate the semiconductor processing and increase the production cost.
The present invention provides a method for programming a multi-level memory cell. When a NROM structure is used to fabricate the multi-level memory cell, it only requires fixing the bias and reading one side of a bit. The fabricating method of the present invention to form a multi-level memory cell is to simplify the semiconductor processing so that, the production cost is reduced.
The present invention provides a method for programming a multi-level NROM cell. The multi-level NROM cell comprises a silicon nitride layer, wherein the silicon nitride layer can locally trap a plurality of charges to form a plurality of charge trapping regions. The charges stored in these charge-trapping regions are the first bit of memory and a second bit of memory, respectively. The charges that are stored in the trapping region as the second bit of memory form an electrical barrier. The level of the threshold current depends on the size of the electrical barrier. The different levels of the threshold currents are thereby used to define the different memory states of the multi-level NROM memory cell.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.